DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 498
DF2367VF33V
Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.9
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Rev.6.00 Mar. 18, 2009 Page 438 of 980
REJ09B0050-0600
Bit
7, 6
5
4
3
2
1
0
Bit Name
–
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Timer Synchronous Register (TSYR)
Initial value
–
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The write value should always be 0.
Timer Synchronization 5 to 0
These bits select whether operation is independent
of or synchronized with other channels.
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by
means of bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
1: TCNT_5 to TCNT_0 performs synchronous
(TCNT presetting /clearing is unrelated to
other channels)
operation (TCNT synchronous presetting/
synchronous clearing is possible)
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