DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 366

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
8.5
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the on-
chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 8.5 shows a flowchart of DTC operation, and table 8.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
Rev.6.00 Mar. 18, 2009 Page 306 of 980
REJ09B0050-0600