DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 182

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.3
The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Area 0 burst ROM interface control register (BROMCRH)
• Area 1 burst ROM interface control register (BROMCRL)
• Bus control register (BCR)
• DRAM control register (DRAMCR)
• DRAM access control register (DRACCR)
Rev.6.00 Mar. 18, 2009 Page 122 of 980
REJ09B0050-0600
Name
Lower column address strobe
Output enable
Wait
Bus request
Bus request acknowledge
Bus request output
Data transfer acknowledge
1 (DMAC)
Data transfer acknowledge
0 (DMAC)
Register Descriptions
Symbol
LCAS
OE
WAIT
BREQ
BACK
BREQO
DACK1
DACK0
I/O
Output
Output
Input
Input
Output
Output
Output
Output
16-bit DRAM space lower column address
Output enable signal for the DRAM space.
Request signal for release of bus to
Acknowledge signal indicating that bus has
External bus request signal used when
Data transfer acknowledge signal for single
Data transfer acknowledge signal for single
Function
strobe signal.
Wait request signal when accessing
external address space.
external bus master.
been released to external bus master.
internal bus master accesses external
address space when external bus is
released.
address transfer by DMAC channel 1.
address transfer by DMAC channel 0.