DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 141

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Exception Source
Reserved for system use
Internal interrupt *
Notes: 1. Lower 16 bits of the address.
4.3
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 13,
Watchdog Timer.
The interrupt control mode is 0 immediately after reset.
4.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 4.1 and 4.2 show examples of the reset sequence.
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
2. Not available in this LSI.
3. Not available in this LSI. It is reserved for system use.
4. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Reset
Reset Exception Handling
Vector Table.
4
Vector Number
30
31
32
118
⎜
Vector Address *
Normal Mode *
H'003C to H'003D
H'003E to H'003F
H'0040 to H'0041
H'00EC to H'00ED
Rev.6.00 Mar. 18, 2009 Page 81 of 980
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Section 4 Exception Handling
2
1
Advanced Mode
H'0078 to H'007B
H'0080 to H'0083
H'01D8 to H'01DB
H'007C to H'007F
REJ09B0050-0600
⎜