DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 247

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit
timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O
port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR
refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in
sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH.
6.6.13
When burst mode is selected on the DRAM interface, the DACK output timing can be selected
with the DDS bit in DRAMCR. When DRAM space is accessed in DMAC single address mode at
the same time, these bits select whether or not burst access is to be performed.
φ
Address bus
RASn (CSn)
UCAS, LCAS
OE (RD)
HWR (WE)
Data bus
Note: n = 2, 3
Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing Is Extended
DMAC Single Address Transfer Mode and DRAM Interface
Software
standby
T
rc3
by 2 States
T
rp1
T
rp2
Rev.6.00 Mar. 18, 2009 Page 187 of 980
T
p
Section 6 Bus Controller (BSC)
DRAM space write
T
r
T
REJ09B0050-0600
c1
T
c2