DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 201

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.10
REFCR specifies DRAM interface refresh control.
Note:
Bit
15
14
13
12
11
*
Bit Name
CMF
CMIE
RCW1
RCW0
−
Refresh Control Register (REFCR)
Only 0 can be written, to clear the flag.
Initial Value
0
0
0
0
0
R/W
R/(W) *
R/W
R/W
R/W
R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
•
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is
performed, this bit is always cleared to 0 and
cannot be modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
When 0 is written to CMF after reading CMF
= 1 while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1
Rev.6.00 Mar. 18, 2009 Page 141 of 980
Section 6 Bus Controller (BSC)
REJ09B0050-0600