DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 202

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 142 of 980
REJ09B0050-0600
Bit
10
9
8
7
6
5
4
Bit Name
RTCK2
RTCK1
RTCK0
RFSHE
CBRM
RLW1
RLW0
Initial Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Refresh Counter Clock Select
These bits select the clock to be used to
increment the refresh counter. When the input
clock is selected with bits RTCK2 to RTCK0,
the refresh counter begins counting up.
000: Count operation halted
001: Count on φ/2
010: Count on φ/8
011: Count on φ/32
100: Count on φ/128
101: Count on φ/512
110: Count on φ/2048
111: Count on φ/4096
Refresh Control
Refresh control can be performed. When
refresh control is not performed, the refresh
timer can be used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
CBR Refresh Control Mode
Selects CBR refreshing performed in parallel
with other external accesses, or execution of
CBR refreshing alone.
0: External access during CAS-before-RAS
1: External access during CAS-before-RAS
Refresh Cycle Wait Control
These bits select the number of wait states to
be inserted in a DRAM interface CAS-before-
RAS refresh cycle. This setting applies to all
areas designated as DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
refreshing is enabled
refreshing is disabled