DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 712
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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Section 25 Power-Down Modes
25.10
Module stop mode can be individually set for each on-chip peripheral module.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. In turn, when the corresponding
MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the
end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, D/A
converter, A/D converter, PWM, and PWMX are retained.
After the reset state is cancelled, all modules other than DTC are in module stop mode.
While an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
25.11
The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a
direct transition is made from high-speed mode to subactive mode, there is no interruption of
program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and
then executing the SLEEP instruction. After a transition, direct transition exception handling
starts.
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set
to 11, and the PSS bit in TSCR (WDT_1) set to 1.
To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in
SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in
SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR
(WDT_1) set to 1.
Rev. 3.00 Mar 21, 2006 page 656 of 788
REJ09B0300-0300
Module Stop Mode
Direct Transitions
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