DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 425

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Legend:
B:
N: BRR setting for baud rate generator (0
n:
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock
input.
Mode
Asynchronous mode
Clocked synchronous mode
:
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
Bit rate (bit/s)
CKS1
0
0
1
1
Bit Rate Register (BRR)
SMR Setting
CKS0
0
1
0
1
n
0
1
2
3
Bit Rate
B =
B =
64
64
Section 15 Serial Communication Interface (SCI and IrDA)
2
2
2n-1
2n-1
N
10
10
6
6
(N+1)
(N+1)
255)
Rev. 3.00 Mar 21, 2006 page 369 of 788
Error
Error (%) = {
—
B
64
2
REJ09B0300-0300
10
2n-1
6
(N+1)
– 1 }
100