DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 711
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
- Current page: 711 of 847
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Section 25 Power-Down Modes
25.9
Subactive Mode
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set
to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if
the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an
interrupt occurs in subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU operates at a low speed based on the subclock and sequentially
executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are
also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to
0.
Subactive mode is exited by the SLEEP instruction, RES pin input, or STBY pin input.
When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in
LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode
and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY
bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1)
set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the
SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit
in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode.
For details of direct transitions, see section 25.11, Direct Transitions.
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until the clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.
Rev. 3.00 Mar 21, 2006 page 655 of 788
REJ09B0300-0300
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