DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 175
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
- Current page: 175 of 847
- Download datasheet (5Mb)
5.8.2
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
5.8.4
When a product, in which a DTC is incorporated, is used in the following settings, the
corresponding flag bit is not automatically cleared even when exception handing, which is a clear
condition, is executed and the bit is held at 1.
1. When DTCEA3 is set to 1(ADI is set to an interrupt source), IRQ4F flag is not automatically
2. When DTCEA2 is set to 1(ICIA is set to an interrupt source), IRQ5F flag is not automatically
3. When DTCEA1 is set to 1(ICIB is set to an interrupt source), IRQ6F flag is not automatically
4. When DTCEA0 is set to 1(OCIA is set to an interrupt source), IRQ7F flag is not automatically
When activation interrupt sources of DTC and IRQ interrupts are used with the above
combinations, clear the interrupt flag by software in the interrupt handling routine of the
corresponding IRQ.
L1:
cleared.
cleared.
cleared.
cleared.
Instructions that Disable Interrupts
Interrupts during Execution of EEPMOV Instruction
Setting on Product Incorporating DTC
EEPMOV.W
MOV.W
BNE
R4,R4
L1
Rev. 3.00 Mar 21, 2006 page 119 of 788
Section 5 Interrupt Controller
REJ09B0300-0300
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