DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 481
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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Bit
5
4
3
Bit Name
MST
TRS
ACKE
Initial Value R/W
0
0
0
R/W
R/W
Description
[MST clearing conditions]
1. When 0 is written by software
2. When lost in bus contention in I
[MST setting conditions]
1. When 1 is written by software (for MST clearing
2. When 1 is written in MST after reading MST = 0 (for
[TRS clearing conditions]
1. When 0 is written by software (except for TRS setting
2. When 0 is written in TRS after reading TRS = 1 (for
3 When lost in bus contention in I
4. When the SW bit in DDCSWR is changed from 1 to 0
[TRS setting conditions]
1. When 1 is written by software (except for TRS clearing
2. When 1 is written in TRS after reading TRS = 0 (for
3. When 1 is received as the R/W bit after the first frame
Acknowledge Bit Decision and Selection
0: The value of the acknowledge bit is ignored, and
1: If the received acknowledge bit is 1, continuous
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
mode
condition 1)
MST clearing condition 2)
condition 3)
TRS setting condition 3)
mode
conditions 3 and 4)
TRS clearing conditions 3 and 4)
address matching in I
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
transfer is halted.
Section 16 I
Rev. 3.00 Mar 21, 2006 page 425 of 788
2
C bus format slave mode
2
C Bus Interface (IIC) (Optional)
2
2
C bus format master
C bus format master
REJ09B0300-0300
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