DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 47

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Figure 19.5
Figure 19.6
Figure 19.7
Figure 19.8
Section 20 D/A Converter
Figure 20.1
Figure 20.2
Section 21 A/D Converter
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Figure 21.7
Figure 21.8
Figure 21.9
Section 23 ROM
Figure 23.1
Figure 23.2
Figure 23.3
Figure 23.4
Figure 23.5
Figure 23.6
Figure 23.7
Figure 23.8
Figure 23.9
Figure 23.10 Programming/Erasing Flowchart Example in User Program Mode..................... 623
Figure 23.11 Program/Program-Verify Flowchart .................................................................... 625
Figure 23.12 Erase/Erase-Verify Flowchart.............................................................................. 627
Figure 23.13 Memory Map in Programmer Mode .................................................................... 630
Section 24 Clock Pulse Generator
Figure 24.1
Figure 24.2
Figure 24.3
Figure 24.4
Power-Down State Termination Timing.............................................................. 571
SERIRQ Timing................................................................................................... 572
Clock Start Request Timing................................................................................. 574
HIRQ Flowchart (Example of Channel 1) ........................................................... 577
Block Diagram of D/A Converter ........................................................................ 579
D/A Converter Operation Example...................................................................... 583
Block Diagram of A/D Converter ........................................................................ 586
Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected)............................................................................................................... 593
A/D Conversion Timing ...................................................................................... 594
External Trigger Input Timing............................................................................. 595
A/D Conversion Accuracy Definitions ................................................................ 597
A/D Conversion Accuracy Definitions ................................................................ 597
Example of Analog Input Circuit......................................................................... 598
Example of Analog Input Protection Circuit ....................................................... 600
Equivalent Circuit of Analog Input Pin ............................................................... 600
Block Diagram of Flash Memory ........................................................................ 604
Flash Memory State Transitions .......................................................................... 605
Boot Mode ........................................................................................................... 606
User Program Mode (Example) ........................................................................... 607
64-Kbyte Flash Memory Block Configuration .................................................... 608
128-Kbyte Flash Memory Block Configuration .................................................. 609
256-Kbyte Flash Memory Block Configuration .................................................. 610
On-Chip RAM Area in Boot Mode...................................................................... 621
ID Code Area ....................................................................................................... 622
Block Diagram of Clock Pulse Generator............................................................ 633
Typical Connection to Crystal Resonator ............................................................ 634
Equivalent Circuit of Crystal Resonator .............................................................. 634
Example of External Clock Input......................................................................... 635
Rev. 3.00 Mar 21, 2006 page xlv of liv