DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 462
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
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Section 15 Serial Communication Interface (SCI and IrDA)
15.9
15.9.1
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 26, Power-Down Modes.
15.9.2
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
15.9.3
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the
mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit
is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To
send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit
to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
15.9.4
Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
15.9.5
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data
is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.
Rev. 3.00 Mar 21, 2006 page 406 of 788
REJ09B0300-0300
Usage Notes
Module Stop Mode Setting
Break Detection and Processing
Mark State and Break Detection
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Relation between Writing to TDR and TDRE Flag
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