DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 571

MCU 3V 128K 144-TQFP

DF2161BVTE10

Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2161BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
Bit
0
Bit Name
FGA20E
Initial
Value
0
Slave
R/W
R/W
Host
Section 18 Host Interface X-Bus Interface (XBS)
Description
Fast A20 Gate Function Enable
When P81DDR=0:
0: XBS fast A20 gate function disabled
1: Setting prohibited
When P81DDR=1:
0: XBS fast A20 gate function disabled
1: XBS fast A20 gate function enabled
When the fast A20 gate is disabled, the normal
A20 gate can be implemented by the firmware
operation of the P81 output.
When the host interface (XBS) fast A20 gate
function is enabled, the DDR bit for P81 must be
set to 1. Therefore, the state of the P81/GA20 pin
cannot be monitored by reading the DR bit for
P81.
A fast A20 gate function is also provided in the
LPC. The state of the P81/GA20 pin can be
monitored by reading the LPC’s GA20 bit.
Rev. 3.00 Mar 21, 2006 page 515 of 788
REJ09B0300-0300

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