R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 88
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 CPU
[Legend]
d:
S:
D:
SD:
S/D:
S:4:
Notes: 1. Only @aa:16 is available.
Rev. 2.00 Sep. 24, 2008 Page 54 of 1468
REJ09B0412-0200
Classifi-
cation
Bit
manipu-
lation
Branch
System
control
d:16 or d:32
Can be specified as a source operand.
Can be specified as a destination operand.
Can be specified as either a source or destination operand or both.
Can be specified as either a source or destination operand.
4-bit immediate data can be specified as a source operand.
2. @ERn+ as a source operand and @−ERn as a destination operand
3. Specified by ER5 as a source address and ER6 as a destination address for data
4. Size of data to be added with a displacement
5. Only @ERn− is available
6. When the number of bits to be shifted is 1, 2, 4, 8, or 16
7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
8. Size of data to specify a branch condition
9. Byte when immediate or register direct, otherwise, word
10. Only @ERn+ is available
11. Only @−ERn is available
12. Only when the multiplier is available.
Instruction
BFLD
BFST
BRA/BS, BRA/BC*
BSR/BS, BSR/BC*
LDC
(CCR, EXR)
LDC
(VBR, SBR)
STC
(CCR, EXR)
STC
(VBR, SBR)
ANDC, ORC,
XORC
SLEEP
NOP
transfer.
register
8
8
Size
B
B
B
B
B/W*
L
B/W*
L
B
—
—
9
9
#xx
S
S
Rn
D
S
S
S
D
D
@ERn @(d,ERn)
S
D
S
S
S
D
S
D
Addressing Mode
@(d,
RnL.B/
Rn.W/
ERn.L)
@−ERn/
@ERn+/
@ERn−/
@+ERn
S*
D*
10
11
@aa:8
S
D
S
S
@aa:16/
@aa:32
S
D
S
S
S
D
—
O
O
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