R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 37
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Classification
CPU
Power on reset (POR) *
Voltage detection circuit
(LVD)*
Interrupt
(source)
Module/
Function
MCU
operating
mode
Interrupt
controller
(INTC)
Break
interrupt
(UBC)
Description
Mode 1: User boot mode
Mode 2: Boot mode
Mode 3: Boundary scan enabled single chip mode
Mode 4: On-chip ROM disabled external extended mode, 16-bit
Mode 5: On-chip ROM disabled external extended mode, 8-bit bus
Mode 6: On-chip ROM enabled external extended mode
Mode 7: Single-chip mode (can be externally extended)
•
•
•
•
•
•
•
•
•
•
Low power consumption state (transition driven by the SLEEP
instruction)
At power-on or low power supply voltage, an internal reset
signal is generated
At low power supply voltage, an internal reset and an interrupt
are generated.
13 external interrupt pins (NMI, and IRQ11 to IRQ0)
Internal interrupt sources
H8SX/1668R Group: 124 pins
H8SX/1668M Group: 125 pins
Two interrupt control modes (specified by the interrupt control
register)
Eight priority orders specifiable (by setting the interrupt priority
register)
Independent vector addresses
Break point can be set for four channels
Address break can be set for CPU instruction fetch cycles
(selected by driving the MD2 and MD1 pins low and
driving the MD0 pin high)
(selected by driving the MD2 and MD0 pins low and
driving the MD1 pin high)
(selected by driving the MD2 pin low and driving the MD1
and MD0 pins high)
bus (selected by driving the MD1 and MD0 pins low and
driving the MD2 pin high)
(selected by driving the MD1 pin low and driving the MD2
and MD0 pins high)
(selected by driving the MD0 pin low and driving the MD2
and MD1 pins high)
(selected by driving the MD2, MD1, and MD0 pins high)
Rev. 2.00 Sep. 24, 2008 Page 3 of 1468
Section 1 Overview
REJ09B0412-0200
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