R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 435
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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10.4
Table 10.4 shows the DMAC transfer modes. The transfer modes can be specified to the
individual channels.
Table 10.4 Transfer Modes
When the auto request setting is selected as the activation source, the cycle stealing or burst access
can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer
counter is stopped and the transfer is continued without the limitation of the transfer count.
Address
Mode
Dual
address
Single
address
Transfer Modes
Transfer mode
•
•
•
Repeat or block size
= 1 to 65,536 bytes,
1 to 65,536 words, or
1 to 65,536
longwords
•
•
•
Normal transfer
Repeat transfer
Block transfer
Instead of specifying the source or destination address
registers, data is directly transferred from/to the external
device using the DACK pin
The same settings as above are available other than address
register setting (e.g., above transfer modes can be specified)
One transfer can be performed in one bus cycle (the types of
transfer modes are the same as those of dual address modes)
Activation Source
•
•
•
Auto request
(activated by
CPU)
On-chip module
interrupt
External request
Common Function
•
•
•
Total transfer
size: 1 to 4
Gbytes or not
specified
Offset addition
Extended repeat
area function
Rev. 2.00 Sep. 24, 2008 Page 401 of 1468
Section 10 DMA Controller (DMAC)
Source
Address Register
DSAR
DSAR/
DACK
REJ09B0412-0200
Destina-
tion
DDAR
DACK/
DDAR
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