R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 620
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 12 Data Transfer Controller (DTC)
12.5.9
Table 12.9 shows the execution status for a single DTC data transfer, and table 12.10 shows the
number of cycles required for each execution.
Table 12.9 DTC Execution Status
[Legend]
P: Block size (CRAH and CRAL value)
Note:
Rev. 2.00 Sep. 24, 2008 Page 586 of 1468
REJ09B0412-0200
Mode
Normal 1
Repeat 1
Block
transfer
1. When transfer information read is skipped
2. In full address mode operation
3. In short address mode operation
4. When the SAR or DAR is in fixed mode
5. When the SAR and DAR are in fixed mode
6. When a longword is transferred while an odd address is specified in the address
7. When a word is transferred while an odd address is specified in the address register or
Vector
Read
I
1
Number of DTC Execution Cycles
register
when a longword is transferred while address 4n + 2 is specified
0*
0*
0*
1
1
1
Transfer
Information
Read
J
4*
4*
4*
2
2
2
3*
3*
3*
3
3
3
0*
0*
0*
1
1
1
Transfer
Information
Write
L
3*
3*
3*
2.3
2.3
2.3
2*
2*
2*
4
4
4
1*
1*
1*
5
5
5
Data Read
L
3*
3*
3•P*
6
6
6
2*
2*
2•P*
7
7
7
1
1
1•P 3•P*
Data Write
M
3*
3*
6
6
6
2*
2*
2•P*
7
7
7
1
1
1•P
Internal
Operation
N
1
1
1
0*
0*
0*
1
1
1
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