R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1017

MCU FLASH 384K ROM 144-LQFP

R5F61663RN50FPV

Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61663RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
5
4
3
2
1
0
Bit Name
EP1 RDFN
EP2 PKTE
EP0s RDFN Undefined W
EP0o RDFN Undefined W
EP0i PKTE
Initial
Value
Undefined W
Undefined W
Undefined 
Undefined W
R/W
Description
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-buffer configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Reserved
The write value should always be 0.
EP0s Read Complete
Write 1 to this bit after data for the EP0s command
FIFO has been read. Writing 1 to this bit enables
transfer of data in the following data stage. A NACK
handshake is returned in response to transfer
requests from the host in the data stage until 1 is
written to this bit.
EP0o Read Complete
Writing 1 to this bit after one packet of data has been
read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet to
be received.
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Rev. 2.00 Sep. 24, 2008 Page 983 of 1468
Section 20 USB Function Module (USB)
REJ09B0412-0200

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