R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 319
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 319 of 1506
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To ensure the row address hold time or read access time, one to three of Trw cycles in which the
row address output is retained can be inserted between the Tr and Tc1 cycles. The RAS signal is
driven low in the Tr cycle and the column address is output in the Tc1 cycle. Set the bit according
to the DRAM to be used and the frequency of this LSI so that the row address hold time to the
rising edge of the RAS signal is ensured.
Figure 9.41 shows an access timing example when one Trw cycle is specified.
Figure 9.41 Access Timing Example when One Trw Cycle is Specified (RAST=0, CAST=0)
Read
Write
Address bus
Data bus
OE (RD)
Data bus
OE (RD)
RD/WR
LUCAS
LLCAS
RAS
WE
WE
BS
Bφ
T
p
Row address
T
r
High
High
T
rw
Rev. 2.00 Sep. 24, 2008 Page 285 of 1468
T
Column address
c1
Section 9 Bus Controller (BSC)
T
c2
REJ09B0412-0200
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