R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 478
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 10 DMA Controller (DMAC)
10.6
Operations on completion of a transfer differ according to the transfer end condition. DMA
transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0.
(1)
When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The
DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the
DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When
the DTCR value is 0 before the transfer, the transfer is not stopped.
(2)
When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer
size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMDR is cleared
to 0 and the ESIF bit in DMDR is set to 1.
• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to
When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0.
A transfer size error is not generated. Operation in each transfer mode is shown below.
• In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data
• In block transfer mode, when the DTCR value is less than the block size, the specified size of
Rev. 2.00 Sep. 24, 2008 Page 444 of 1468
REJ09B0412-0200
transfer is disabled due to the DTCR value less than the data access size
the DTCR value less than the block size
access size, data is transferred in bytes
data in DTCR is transferred instead of transferring the block size of data. The transfer is
performed in bytes.
Transfer End by DTCR Change from 1, 2, or 4, to 0
Transfer End by Transfer Size Error Interrupt
DMA Transfer End
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