R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1315
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 28 Power-Down Modes
28.10
Sleep Instruction Exception Handling
A sleep instruction exception handling is generated by executing a SLEEP instruction. The sleep
instruction exception handling is always accepted in the program execution state.
When the SLPIE bit is set to 0, sleep instruction exception handling does not follow execution of
the SLEEP instruction. In this case, the CPU is placed in the power-down state. After exit from the
power-down state has been initiated by an exception, the CPU starts handling of the exception.
When the SLPIE bit is set to 1, sleep instruction exception handling follows execution of the
SLEEP instruction. The CPU immediately starts sleep instruction exception handling, which
blocks the transition to the power-down state is prevented by.
When a SLEEP instruction is executed while the SLPIE bit is cleared to 0, a transition is made to
the power-down state. Exit from the power-down state is initiated by an exit-initiating interrupt
source (see figure 28.10).
When an interrupt that causes exit from the power-down state is generated immediately before the
execution of a SLEEP instruction, exception handling for the interrupt starts. On return from the
exception service routine, the SLEEP instruction is executed to enter the power-down state. In this
case, exit from the power-down state will not take place until the next time an exit-initiating
interrupt is generated (see figure 28.11).
As stated above, setting the SLPIE bit to 1 causes sleep instruction exception handling to follow
the execution of the SLEEP instruction. If this setting is made in the exception service routine for
an interrupt that initiates exit from the power-down state, handling of the sleep instruction
exception due to the execution of a SLEEP instruction will proceed even if the interrupt was
generated immediately beforehand (see figure 28.12). Consequently, the CPU will execute the
instruction that follows the SLEEP instruction, after handling of the sleep instruction exception
and exception service routine, and will not enter the power-down state.
Thus, when the SLPIE bit is set to 1 to enable the sleep exception handling, clear the SSBY bit in
SBYCR to 0.
Rev. 2.00 Sep. 24, 2008 Page 1281 of 1468
REJ09B0412-0200
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