R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 41
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Classification
Timer
Watchdog timer Watchdog
32K timer
Module/
Function
16-bit timer
pulse unit
(TPU)
Program-
mable pulse
generator
(PPG)
timer
(WDT)
32K timer
(TM32K)
Description
•
•
•
•
•
•
•
Note: *
•
•
•
Notes: 1. Pulse output pins PO31 to PO16 cannot be activated by
•
•
•
•
•
•
16 bits × 12 channels (unit 0, unit 1*)
Select from among eight counter-input clocks for each channel
Up to 16 pulse inputs and outputs
Counter clear operation, simultaneous writing to multiple timer
counters (TCNT), simultaneous clearing by compare match and
input capture possible, simultaneous input/output for registers
possible by counter synchronous operation, and up to 15-phase
PWM output possible by combination with synchronous
operation
Buffered operation, cascaded operation (32 bits × two
channels), and phase counting mode (two-phase encoder
input) settable for each channel
Input capture function supported
Output compare function (by the output of compare match
waveform) supported
32-bit*
Four output groups, non-overlapping mode, and inverted output
can be set
Selectable output trigger signals; the PPG can operate in
conjunction with the data transfer controller (DTC) and the DMA
controller (DMAC)
8 bits × one channels (selectable from eight counter input
clocks)
Switchable between watchdog timer mode and interval timer
mode
Eight counter clocks which divides the 32.768 Hz clock can be
selected
8 bits × 1 channel or 24 bits × 1 channel can be selected
Interrupts can be generated when the counter overflows.
Eight overflow cycles selectable (250 msec, 500 msec, 1 sec, 2
sec, 30 sec, 60 sec, about 23 days, and about 46 days)
2. Pulse of unit 1 cannot be output in external bus
1
*
Pin function of unit 1 cannot be used in the external bus
extended mode.
input capture.
extended mode.
2
pulse output
Rev. 2.00 Sep. 24, 2008 Page 7 of 1468
Section 1 Overview
REJ09B0412-0200
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