R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 38
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 1 Overview
Rev. 2.00 Sep. 24, 2008 Page 4 of 1468
REJ09B0412-0200
Classification
DMA
External bus
extension
Module/
Function
EXDMA
controller
(EXDMAC)
DMA
controller
(DMAC)
Data
transfer
controller
(DTC)
Bus
controller
(BSC)
Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Four-channel DMA transfer available
Two activation methods (auto-request and external request)
Four transfer modes (normal, repeat, block, and cluster
transfer)
Dual or single address mode selectable
Extended repeat area function
Four-channel DMA transfer available
Three activation methods (auto-request, on-chip module
interrupt, and external request)
Three transfer modes (normal, repeat, and block)
Dual or single address mode selectable
Extended repeat area function
Allows DMA transfer over 78 channels (number of DTC
activation sources)
Activated by interrupt sources (chain transfer enabled)
Three transfer modes (normal transfer, repeat transfer, block
transfer)
Short-address mode or full-address mode selectable
16-Mbyte external address space
The external address space can be divided into eight areas,
each of which is independently controllable
Chip-select signals (CS0 to CS7) can be output
Access in two or three states can be selected for each area
Program wait cycles can be inserted
The period of CS assertion can be extended
Idle cycles can be inserted
Bus arbitration function (arbitrates bus mastership among the
internal CPU, DMAC, EXDMAC, DTC, Refresh, and external
bus masters)
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