R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 807
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.10.11 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 14.54 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
14.10.12 Conflict between TCNT Write and Overflow/Underflow
If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 14.55 shows the operation timing when there is conflict between TCNT write and
overflow.
Figure 14.54 Conflict between Overflow and Counter Clearing
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF flag
TCFV flag
Figure 14.55 Conflict between TCNT Write and Overflow
Pφ
Address
Write
TCNT
TCFV flag
H'FFFF
Disabled
H'FFFF
TGR write cycle
T
TCNT address
1
T
2
H'0000
Rev. 2.00 Sep. 24, 2008 Page 773 of 1468
Section 14 16-Bit Timer Pulse Unit (TPU)
M
TCNT write data
REJ09B0412-0200
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