R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 404
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Bus Controller (BSC)
• Transfers are continued without bus release when a bus master with priority over the DMAC is
A transfer other than the above is stopped and the bus is passed when the bus cycle is completed.
However, the EXDMAC takes control of the bus and EXDMAC transfers are continued when
multiple channels in the EXDMAC request the bus while other bus masters are not requesting the
bus.
(5)
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in
BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
(6)
When area 2 is specified as the DRAM space or SDRAM space with the RFSHE bit in REFCR set
to 1, RTCNT starts to count up. When the RTCOR value matches RTCNT, a bus request is sent to
the bus arbiter.
A refresh cycle is inserted on completion of the external bus cycle. A refresh cycle is not
consecutively inserted. Once a refresh cycle is inserted, the bus is passed to another bus master.
When the bus is passed, if there is no bus request from other bus masters, NOP cycles are inserted.
Rev. 2.00 Sep. 24, 2008 Page 370 of 1468
REJ09B0412-0200
not requesting the bus, the EBCCS bit in BCR2 is cleared to 0, and either the following
conditions are executed.
While one block of data is being transferred in block transfer mode
While data is being transferred in burst mode
External Bus Release
Refresh
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