R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 841
![MCU 256K FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24268NVFQV
Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
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Manufacturer:
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H8S/2426, H8S/2426R, H8S/2424 Group
• NDRLH*
• NDRLL*
Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7
6
5
4
3 to 0
Bit
7 to 4
3
2
1
0
Bit Name
⎯
NDR3
NDR2
NDR1
NDR0
Bit Name
NDR7
NDR6
NDR5
NDR4
⎯
NDRH address is H'FF4C. When they have different output triggers, the NDRH
addresses corresponding to the groups 2 and 3 are NDRHL (H'FF4E) and NDRHH
(H'FF4C), respectively. Also, when pulse output groups 0 and 1 have the same output
trigger by PCR settings, the NDRL address is H'FF4D. When they have different
output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL
(H'FF4F) and NDRLH (H'FF4D), respectively.
Initial Value
0
0
0
0
All 1
Initial Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
⎯
R/W
⎯
R/W
R/W
R/W
R/W
Description
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
1 is always read and write is disabled.
Description
Reserved
1 is always read and write is disabled.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Section 12 Programmable Pulse Generator (PPG)
Page 811 of 1372
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