R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 268

MCU 256K FLASH 48K 144-LQFP

R4F24268NVFQV

Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
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Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 6 Bus Controller (BSC)
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.7.9, Wait Control.
(2)
Even when burst operation is selected, it may happen that access to DRAM space is not
continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low
during the access to the other space, burst operation can be resumed when the same row address in
DRAM space is accessed again.
• RAS Down Mode
Page 238 of 1372
Note: n = 2 to 5
Read
Write
To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the RAS signal is held low
during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.44 shows an example of the timing in RAS down mode.
RAS Down Mode and RAS Up Mode
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Figure 6.43 Operation Timing in Fast Page Mode
T
Row address
p
T
r
(RAST = 0, CAST = 1)
High
High
T
c1
Column address 1
T
c2
T
c3
H8S/2426, H8S/2426R, H8S/2424 Group
T
c1
Column address 2
REJ09B0466-0350 Rev. 3.50
T
c2
Jul 09, 2010
T
c3

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