R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 1076

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1046 of 1372
Bit
3
2
1
Bit Name
TEND
TDRE
RDRF
Initial
Value
1
1
0
R/W
R
R/W
R/W
Description
Transmit End
[Setting condition]
•
•
[Clearing conditions]
•
•
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
•
[Clearing conditions]
•
•
When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
When writing 0 after reading TEND = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When writing data to SSTDR
When the TE bit in SSER is 0
When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
When writing 0 after reading TDRE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When writing data to SSTDR with TE = 1
When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
When writing 0 after reading RDRF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When reading receive data from SSRDR
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010