R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 24

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
16.1 Features.............................................................................................................................. 955
16.2 Input/Output Pins............................................................................................................... 957
16.3 Register Descriptions ......................................................................................................... 958
16.4 Operation ........................................................................................................................... 971
16.5 Interrupt Request................................................................................................................ 986
16.6 Bit Synchronous Circuit..................................................................................................... 987
16.7 Usage Notes ....................................................................................................................... 988
Section 17 A/D Converter ................................................................................. 991
17.1 Features.............................................................................................................................. 991
17.2 Input/Output Pins............................................................................................................... 994
17.3 Register Descriptions ......................................................................................................... 996
17.4 Operation ......................................................................................................................... 1008
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16.3.1 I
16.3.2 I
16.3.3 I
16.3.4 I
16.3.5 I
16.3.6 Slave Address Register (SAR).............................................................................. 969
16.3.7 I
16.3.8 I
16.3.9 I
16.4.1 I
16.4.2 Master Transmit Operation................................................................................... 972
16.4.3 Master Receive Operation .................................................................................... 974
16.4.4 Slave Transmit Operation ..................................................................................... 976
16.4.5 Slave Receive Operation....................................................................................... 979
16.4.6 Noise Canceler...................................................................................................... 981
16.4.7 Example of Use..................................................................................................... 981
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 997
17.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0)............................................ 999
17.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1).......................................... 1001
17.3.4 A/D Control Register (ADCR_0) Unit 0 ............................................................ 1004
17.3.5 A/D Control Register (ADCR_1) Unit 1 ............................................................ 1006
17.4.1 Single Mode........................................................................................................ 1008
17.4.2 Scan Mode .......................................................................................................... 1010
17.4.3 Input Sampling and A/D Conversion Time ........................................................ 1014
17.4.4 External Trigger Input Timing............................................................................ 1016
2
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ................................................................... 960
C Bus Control Register B (ICCRB) ................................................................... 962
C Bus Mode Register (ICMR)............................................................................ 963
C Bus Interrupt Enable Register (ICIER)........................................................... 965
C Bus Status Register (ICSR)............................................................................. 967
C Bus Transmit Data Register (ICDRT) ............................................................ 970
C Bus Receive Data Register (ICDRR).............................................................. 970
C Bus Shift Register (ICDRS)............................................................................ 970
C Bus Format...................................................................................................... 971
C Bus Interface 2 (IIC2)................................................................ 955