R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 324

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
(7)
Note: The DRAM interface is not supported by the 5-V version.
(a)
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show examples of
idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if
bits ICIS1 and ICIS0 are set to 1.
Page 294 of 1372
Idle Cycle in Case of Normal Space Access after DRAM Space Access
Normal space access after DRAM space read access
UCAS, LCAS
Address bus
Data bus
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
RAS
Figure 6.88 Example of Idle Cycle Operation after DRAM Access
RD
φ
T
p
DRAM space read
T
r
T
c1
T
c2
Idle cycle
External address space read
T
i
T
1
T
2
T
H8S/2426, H8S/2426R, H8S/2424 Group
3
DRAM space read
T
i
REJ09B0466-0350 Rev. 3.50
T
c1
T
c2
Jul 09, 2010