R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 832

MCU 256K FLASH 48K 144-LQFP

R4F24268NVFQV

Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.54 shows the operation timing when there is contention between TCNT write and
overflow.
11.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, the TCLKD input pin
with the TIOCB2 I/O pin, the TCLKE input pin with the TIOCC6 I/O pin, the TCLKF input pin
with the TIOCD6 I/O pin, the TCLKG input pin with the TIOCB7 I/O pin, and the TCLKH input
pin with the TIOCB8 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
11.10.14 Interrupts and Module Stop Mode
If a transition is made to the module stop state when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts
should therefore be disabled before entering the module stop state.
Page 802 of 1372
Figure 11.54 Contention between TCNT Write and Overflow
φ
Address
Write signal
TCNT
TCFV flag
H'FFFF
TCNT write cycle
T
TCNT address
2
1
state of a TCNT write cycle, when
T
2
M
H8S/2426, H8S/2426R, H8S/2424 Group
TCNT write data
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010

Related parts for R4F24268NVFQV