HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 433

• Manufacturer Part Number: HD64F2218TF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218TF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be
written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bits in SSR
have different functions in normal mode and smart card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
Bit Name Initial Value R/W
TDRE
RDRF
Serial Status Register (SSR)
1
0
R/(W)*
R/(W)*
1
1
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive data is
transferred from RSR to RDR
[Clearing conditions]
•
•
RDR and the RDRF flag are not affected and retain their
previous values when the RE bit in SCR is cleared to 0.
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data
can be written to TDR
When 0 is written to TDRE after reading TDRE = 1*
When the DMAC is activated by a TXI interrupt
request and writes data to TDR
When 0 is written to RDRF after reading RDRF = 1*
When the DMAC is activated by an RXI interrupt and
transferred data from RDR
Rev.7.00 Dec. 24, 2008 Page 377 of 698
REJ09B0074-0700
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