HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 532
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Note:* When DMA writes are enabled (EP2T1 set to 1 and EP2T0 set to 0 or 1 in UDMAR), it is not
14.3.6
UESTL0 is used to forcibly stall each endpoint EP0 to EP3. When the bit is set to 1, the
corresponding endpoint returns a stall handshake to the host, following from the next transfer.
The stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for
which decoding is performed by the function, and thus the EP0STL bit is cleared to 0. When the
SetupTS flag in UIFR0 is set to 1, a write of 1 to the EP0STL bit is ignored. For details, refer to
section 14.5.9, Stall Operations.
Rev.7.00 Dec. 24, 2008 Page 476 of 698
REJ09B0074-0700
Bit
0
Bit
7, 6
5
4
3
2, 1
0
Bit Name
—
Bit Name
—
EP2STL
EP1STL
EP3STL
—
EP0STL
possible to clear the data in the FIFO by writing 1 to EP2CLR. To clear the data in the FIFO,
disable DMA transfers (clear EP2T1 and EP2T0 in UDMAR to 0) and then write 1 to
EP2CLR.
USB Endpoint Stall Register 0 (UESTL0)
Initial Value R/W
0
Initial Value R/W
All 0
0
0
0
All 0
0
R
R
R/W
R/W
R/W
R
R/W
Description
Reserved
This bit is always read as 0 and cannot be modified.
Description
Reserved
These bits are always read as 0 and cannot be
modified.
EP2 Stall
0: Cancels the EP2 stall state.
1: Sets the EP2 stall state.
EP1 Stall
0: Cancels the EP1 stall state.
1: Sets the EP1 stall state.
EP3 Stall
0: Cancels the EP3 stall state.
1: Sets the EP3 stall state.
Reserved
These bits are always read as 0 and cannot be
modified.
EP0 Stall
0: Cancels the EP0 stall state.
1: Sets the EP0 stall state.
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