HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 393
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T
precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.53 shows the operation timing
when there is contention between TCNT write and overflow.
Multiplexing of I/O Pins: In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O
pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O
pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare
match output should not be performed from a multiplexed pin.
Interrupts in Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Module Stop Mode Setting: TPU operation can be disabled or enabled using the module stop
control register. The initial setting is for TPU operation to be halted. Register access is enabled by
clearing module stop mode. For details, refer to section 20, Power-Down Modes.
2
state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes
Address
Write signal
TCNT
TCFV flag
Figure 9.53 Contention between TCNT Write and Overflow
φ
H'FFFF
Prohibited
TCNT write cycle
TCNT address
T
1
T
2
Rev.7.00 Dec. 24, 2008 Page 337 of 698
M
TCNT write data
REJ09B0074-0700
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