HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 508
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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13.3
The boundary scan function has the following registers. These registers cannot be accessed by the
CPU.
• Instruction register (INSTR)
• IDCODE register (IDCODE)
• BYPASS register (BYPASS)
• Boundary scan register (BSCANR)
13.3.1
INSTR is a 3-bit register. At initialization, this register is specified to IDCODE mode. When
TRST is pulled low, or when the TAP controller is in the Test-Logic-Reset state, INSTR is
initialized. INSTR can be written by the serial data input from the TDI. If more than three bits of
instruction is input from the TDI, INSTR stores the last three bits of serial data.
If a command reserved in INSTR is used, the correct operation cannot be guaranteed.
Table 13.2 Instruction Configuration
Rev.7.00 Dec. 24, 2008 Page 452 of 698
REJ09B0074-0700
Bit
2
1
0
Bit 2
TI2
0
0
0
0
1
1
1
1
Bit Name
TI2
TI1
TI0
Instruction Register (INSTR)
Register Descriptions
Bit1
TI1
0
0
1
1
0
0
1
1
Initial Value R/W
1
0
1
Bit 0
TI0
0
1
0
1
0
1
0
1
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
Reserved
IDCODE (initial value)
Reserved
BYPASS
—
—
—
Test Instruction Bits
Instruction configuration is shown in table 13.2.
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