HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 252

• Manufacturer Part Number: HD64F2218TF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218TF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.4.8
An example of the basic DMAC bus cycle timing is shown in figure 7.14. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
Rev.7.00 Dec. 24, 2008 Page 196 of 698
REJ09B0074-0700
Basic DMAC Bus Cycles
CPU cycle
φ
Address bus
RD
HWR
LWR
Figure 7.14 Example of DMA Transfer Bus Timing
T
Source
address
1
T
DMAC cycle (1-word transfer)
2
T
1
Destination address
T
2
T
3
T
1
T
2
T
3
CPU cycle