MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 421

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WOMQ — Wired-OR Mode for QSPI Pins
BITS[3:0] — Bits Per Transfer
CPOL — Clock Polarity
CPHA — Clock Phase
M68HC16 Z SERIES
USER’S MANUAL
In master mode, when BITSE is set in a command RAM byte, BITS[3:0] determines
the number of data bits transferred. When BITSE is cleared, eight bits are transferred.
Reserved values default to eight bits. In slave mode, the command RAM is not used
and the setting of BITSE has no effect on QSPI transfers. Instead, the BITS[3:0] field
determines the number of bits the QSPI will receive during each transfer before storing
the received data.
Table D-35
CPOL is used to determine the inactive state of the serial clock (SCK). It is used with
CPHA to produce a desired clock/data relationship between master and slave devices.
CPHA determines which edge of SCK causes data to change and which edge causes
data to be captured. CPHA is used with CPOL to produce a desired clock/data rela-
tionship between master and slave devices.
0 = Pins designated for output by DDRQS operate in normal mode.
1 = Pins designated for output by DDRQS operate in open-drain mode.
0 = The inactive state of SCK is logic zero.
1 = The inactive state of SCK is logic one.
0 = Data is captured on the leading edge of SCK and changed on the trailing edge
1 = Data is changed on the leading edge of SCK and captured on the trailing edge
of SCK.
of SCK
shows the number of bits per transfer.
Freescale Semiconductor, Inc.
For More Information On This Product,
BITS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table D-35 Bits Per Transfer
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REGISTER SUMMARY
Bits Per Transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16
10
11
12
13
14
15
8
9
D-47