MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 174

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9.3 Using Chip-Select Signals for Interrupt Acknowledge
5-68
Ordinary bus cycles use supervisor or user space access, but interrupt acknowledge
bus cycles use CPU space access. Refer to
rupts
type of space, but base and option registers must be properly programmed for each
type of external bus cycle.
During a CPU space cycle, bits [15:3] of the appropriate base register must be config-
ured to match ADDR[23:11], as the address is compared to an address generated by
the CPU. ADDR[23:20] follow the state of ADDR19 in this MCU. The states of base
register bits [15:12] must match that of bit 11.
Figure 5-23
are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority,
and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge
code. The rest of the address lines are set to one.
Because address match logic functions only after the EBI transfers an interrupt ac-
knowledge cycle to the external address bus following IARB contention, chip-select
logic generates AVEC or DSACK signals only in response to interrupt requests from
external IRQ pins. If an internal module makes an interrupt request of a certain priority,
and the chip-select base address and option registers are programmed to generate
AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority
level, chip-select logic does not respond to the interrupt acknowledge cycle, and the
internal module supplies a vector number and generates an internal DSACK signal to
terminate the cycle.
Perform the following operations before using a chip select to generate an interrupt ac-
knowledge signal.
1. Program the base address field to all ones.
2. Program block size to no more than 64 Kbytes, so that the address comparator
3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as
for more information. There are no differences in flow for chip selects in each
checks ADDR[19:16] against the corresponding bits in the base address regis-
ter. (The CPU16 places the CPU space bus cycle type on ADDR[19:16].)
a read cycle.
Figure 5-23 CPU Space Encoding for Interrupt Acknowledge
ACKNOWLEDGE
INTERRUPT
shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]
Freescale Semiconductor, Inc.
FUNCTION
1 1 1
2
CODE
For More Information On This Product,
0
SYSTEM INTEGRATION MODULE
23
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Go to: www.freescale.com
CPU SPACE
TYPE FIELD
19
16
ADDRESS BUS
5.6.4 CPU Space Cycles
LEVEL
0
1
M68HC16 Z SERIES
USER’S MANUAL
and
5.8 Inter-
CPU SPACE IACK TIM