MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 213

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1.2 Freeze Operation
9.2.1.3 QSM Interrupts
M68HC16 Z SERIES
USER’S MANUAL
The freeze FRZ[1:0] bits in QSMCR are used to determine what action is taken by the
QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU16
enters background debug mode. At the present time, FRZ0 has no effect; setting
FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE asser-
tion. Refer to
ground debug mode.
Both the QSPI and SCI can generate interrupt requests. Each has a separate interrupt
request priority register. A single vector register is used to generate exception vector
numbers.
The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and
SCI interrupt requests. The values in these fields correspond to internal interrupt re-
quest signals IRQ[7:1]. A value of %111 causes IRQ7 to be asserted when a QSM in-
terrupt request is made. Lower field values cause correspondingly lower-numbered
interrupt request signals to be asserted. Setting the ILQSPI or ILSCI field values to
%000 disables interrupts for the QSPI and the SCI respectively. If ILQSPI and ILSCI
have the same non-zero value, and the QSPI and SCI make simultaneous interrupt
requests, the QSPI has priority.
When the CPU16 acknowledges an interrupt request, it places the value in the condi-
tion code register interrupt priority (IP) mask on ADDR[3:1]. The QSM compares the
IP mask value to the priority of the interrupt request to determine whether it should
contend for arbitration. QSM arbitration priority is determined by the value of the IARB
field in QSMCR. Each module that can generate interrupt requests must have a non-
zero IARB value, otherwise the CPU16 will identify any such interrupt requests as spu-
rious and take a spurious interrupt exception. Arbitration is performed by means of se-
rial contention between values stored in individual module IARB fields.
When the QSM wins interrupt arbitration, it responds to the CPU16 interrupt acknowl-
edge cycle by placing an interrupt vector number on the data bus. The vector number
is used to calculate displacement into the CPU16 exception vector table. SCI and
QSPI vector numbers are generated from the value in the QIVR INTV field. The values
of bits INTV[7:1] are the same for both the QSPI and the SCI. The value of INTV0 is
supplied by the QSM when an interrupt request is made. INTV0 = 0 for SCI interrupt
requests; INTV0 = 1 for QSPI interrupt requests.
At reset, INTV[7:0] is initialized to $0F, the uninitialized interrupt vector number. To en-
able interrupt-driven serial communication, a user-defined vector number must be writ-
ten to QIVR, and interrupt handler routines must be located at the addresses pointed
to by the corresponding vector. Writes to INTV0 have no effect. Reads of INTV0 return
a value of one.
Refer to
TEGRATION MODULE
SECTION 4 CENTRAL PROCESSOR UNIT
4.14.4 Background Debug Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
for more information about exceptions and interrupts.
QUEUED SERIAL MODULE
Go to: www.freescale.com
for more information about back-
and
SECTION 5 SYSTEM IN-
9-3