MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 162

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.7.8 Use of the Three-State Control Pin
5-56
CLKOUT
CYCLES
RESET
NOTES:
V
LOCK
VCO
BUS
1. INTERNAL START-UP TIME
2. FIRST INSTRUCTION FETCHED
DD
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 5-20
RESET, V
Asserting the three-state control (TSC) input causes the MCU to put all output drivers
in a disabled, high-impedance state. The signal must remain asserted for approxi-
mately ten clock cycles in order for drivers to change state.
When the internal clock synthesizer is used (MODCLK held high during reset), synthe-
sizer ramp-up time affects how long the ten cycles take. Worst case is approximately
20 milliseconds from TSC assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to
high-impedance state as soon after TSC assertion as approximately ten clock pulses
have been applied to the EXTAL pin.
BUS STATE
UNKNOWN
DD
DD
ramp time and VCO frequency ramp time determine how long the four cy-
is a timing diagram for power-on reset. It shows the relationships between
, and bus signals.
2 CLOCKS
Freescale Semiconductor, Inc.
CONTROL SIGNALS
For More Information On This Product,
THREE-STATED
ADDRESS AND
Figure 5-20 Power-On Reset
SYSTEM INTEGRATION MODULE
512 CLOCKS
Go to: www.freescale.com
10 CLOCKS
1
M68HC16 Z SERIES
USER’S MANUAL
2
16 POR TIM