ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 9

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 1 : Pin Description (continued)
P1H.0 - P1H.7
P1L.0 - P1L.7
V
RSTOUT
Symbol
RSTIN
XTAL1
XTAL2
V
PP
V
NMI
V
V
AGND
AREF
DD
/RPD
SS
109, 126,
110, 127,
136, 144
139, 143
118-125
128-135
17,46,
56,72,
82,93,
18,45,
55,71,
83,94,
132
133
134
135
138
137
140
141
142
Pin
37
38
84
Type
I/O
O
O
I
I
I
I
I
I
I
-
-
-
-
-
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. Port1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a demultiplexed bus mode
to a multiplexed bus mode.
The following Port1 pins have alternate functions:
P1H.4
P1H.5
P1H.6
P1H.7
XTAL1
XTAL2:
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a speci-
fied duration while the oscillator is running resets the ST10F168. An internal pullup
resistor permits power-on reset using only a capacitor connected to V
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
Internal Reset Indication Output. This pin is set to a low level during hardware, soft-
ware or watchdog timer reset.
ization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power down) instruction is executed, the NMI pin must be low in order to
force the ST10F168 to go into power down mode. If NMI is high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If it is not used, pin NMI should be pulled high externally.
A/D converter reference voltage.
A/D converter reference ground.
Flash programming voltage. Programming voltage of the on-chip Flash memory
must be supplied to this pin.
It is used also as the timing pin for the return from interruptible powerdown mode.
Digital Supply Voltage:
= + 5V during normal operation and idle mode.
> 2.5V during power down mode.
Digital Ground.
CC24IO
CC25IO
CC26IO
CC27IO
Oscillator amplifier and internal clock generator input
Oscillator amplifier circuit output.
CAPCOM2: CC24 Capture Input
CAPCOM2: CC25 Capture Input
CAPCOM2: CC26 Capture Input
CAPCOM2: CC27 Capture Input
RSTOUT
Function
remains low until the EINIT (end of initial-
SS
ST10F168
. In bidirec-
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