ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 38

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
17.2 - Synchronous Reset (Warm Reset)
A synchronous reset is triggered when
is pulled low while V
to properly activate the internal reset logic of the
MCU, the
during 4 TCL (2 periods of CPU clock). The I/O
pins are set to high impedance and
driven low. After
duration of 12 TCL (approximately 6 periods of
CPU clock) elapes, during which pending internal
hold states are cancelled and the current internal
access cycle if any is completed. External bus
cycle is aborted. The internal pulldown of
pin is activated if bit BDRSTEN of SYSCON reg-
ister was previously set by software. This bit is
Figure 10 : Synchronous Warm Reset: Short low pulse on
Notes: 1. RSTIN assertion can be released there.
38/74
2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the
asynchronous reset is then immediately entered.
3. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
4) RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SUSCON register) was previously set by software. Bit BDRSTE N is cleared after
reset.
CPU
CPU Clock
RSTIN
V
RSTOUT
ALE
Port0
Internal
Reset
Signal
PP
= f
RSTIN
XTAL
/ 2) , else it is 4 CPU clock cycles (8 TCL).
RSTIN
pin must be held low, at least,
4 TCL 12 TCL
min.
PP
200 A Discharge
pin is at high level. In order
level is detected, a short
1
max.
RSTOUT
Internally pulled low
Reset Configuration
RSTIN
Latching point of Port0
for systemstart-up configuration
RSTIN
pin is
pin
1024 TCL
4
always cleared on power-on or after a reset
sequence.
Exit of Synchrounous Reset State
The internal reset sequence starts for 1024 TCL
(512 periods of CPU clock) and
sampled. The reset sequence is extended until
RSTIN
restarts. The system configuration is latched from
Port0 and ALE, RD and R/W pins are driven to
their inactive level. The MCU starts program exe-
cution from memory location 00’0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timing of
synchronous reset sequence are summarized in
Figure 10 and 11.
RSTIN
2
6 or 8 TCL
V
PP
level becomes high. Then, the MCU
> 2.5V AsynchronousReset not entered.
3
RSTIN
INST #1
pin level is