ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 40

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ST10F168SQ6

Manufacturer Part Number
ST10F168SQ6
Description
MCU 256KB FLASH 12K RAM 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheets

Specifications of ST10F168SQ6

Core Processor
ST10
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-MQFP, 144-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST10F168SQ6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F168SQ6 ST10F168-Q3
Manufacturer:
ST
0
ST10F168
The simplest way to reset the ST10F168 is to
insert a capacitor C1 between
and a capacitor between V
with a pullup resistor R0 between V
V
device equalling a resistor of 50k to 150k (the
minimum reset time must be determined by the
lowest value). Select C1 that produce a sufficient
discharge time to permit the internal or external
oscillator and / or internal PLL to stabilize.
To insure correct power-up reset with controlled
supply current consumption, specially if clock sig-
nal requires a long period of time to stabilized, an
asynchronous hardware reset is required during
power-up. It is recommended to connect the exter-
nal R0C0 circuit shown in Figure 12 to the V
pin. On power-up, the logical low level on V
forces an asynchronous harware reset when
RSTIN
The external pullup R0 will then charge the capac-
itor C0. Note that an internal pulldown device on
V
causes the external capacitor (C0) to begin dis-
charging at a typical rate of 100 A to 200 A. With
this mechanism, after power-up reset, short low
pulses applied on
hardware reset. If
Figure 13 : Internal (simplified) Reset Circuitry
40/74
CC
PP
. The input
pin is turned on when
is asserted.
Internal
Reset
Signal
RSTIN
RSTIN
RSTIN
provides an internal pullup
EINIT Instruction
is asserted longer than
produce synchronous
RSTIN
PP
RSTIN
pin and V
Reset State
Machine
pin is low, and
Clock
Clr
Trigger
pin and V
PP
Asynchronous
Reset
Reset Sequence
(512 CPU Clock Cycles)
pin and
SS
PP
Set
Clr
V
(C0)
From/to Exit
Powerdown
Circuit
PP
SS
pin
PP
Q
(Flash device)
,
SRST instruction
watchdog overflow
the time needed for C0 to be discharged by the
internal pulldown device, then the device is forced
in an asynchronous reset. This mechanism
insures recovery from very catastrophic failure.
Figure 12 : Minimum External Reset Circuitry
ST10F168
BDRSTEN
RSTOUT
RSTIN
V
PP
+
+
V
CC
V
V
C1
R0
C0
CC
CC
WeakPulldown
(~200 A)
RSTOUT
External Hardware
(and Interruptible
Power-down
mode)
b) For Power-up
Reset
RSTIN
V
PP
a) Hardware
Reset

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