ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 14

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
5.1 - Programming / Erasing with ST
Embedded Algorithm Kernel
There are three stages to run STEAK :
– To load the registers R0 to R4 with the STEAK
– To initiate the Unlock Sequence. The Unlock Se-
Table 4 : STEAK parameters
Table 5 : Programming / erasing code definition
14/74
Single Word programming
Double Word programming
Multiple (block) programming
Sector Erasing
Set Flash Protection UPROG bit
Read Status
s
AddOff
W
DWL,DWH Data (double Word, DHL = low Word, DWH = high Word) to be written in Flash.
BegAddOff
EndAddOff
SourceAdd
Bnk
2TCL
command, the address and the data to be pro-
gramed, or sector to be erased. Table 4 gives
the STEAK parameters for each type of Flash
programming / erasing operation. Table 5 de-
fines the codes used in Table 4.
quence is composed of two consecutive writes
to an even address in the Flash active address
space - the first write has direct addressing
mode (MOV mem, Rwn) - the second write has
indirect addressing mode (MOV [Rwm], Rwn).
Rwn can be any unused Word-GPR (R6 to R15)
loaded with a value resulting in the same even
address as “mem”.
Command
Segment of the Target Flash Memory cell,
Segment Offset of the Target Flash Memory cell. Must be even value (Word-aligned address).
Data (Word) to be written in Flash.
Segment Offset of the FIRST Target Flash Memory Word to be written in a Multiple programming
command. Must be even value (Word-aligned address).
Segment Offset of the LAST Target Flash Memory Word to be written in a Multiple programming
command.
Must be even value (Word-aligned address). The value D = (EndAddOff - BegAddOff) must be:
0 <= D < 16384 (ie. up to one page (16K Byte) can be written in the flash with one multi-Word
programming command).
Start address for the block to be programmed.
This address is using implicitly the data paging mechanism of the CPU. SourceAdd value must respect
the following rules :
- SourceAdd + (EndAddOff - BegAddOff) < 16384.
- Page 0 and 1 can NOT be used for source data if bit ROMS1 = ‘1’ (in SYSCON register).
Note that source data can be located in Flash (In pages 0, 1, 6 to 19 if bit ROMS1 = ‘0’, or in pages 4 to 19
if bit ROMS1 = ‘1’).
Number of the Bank to be erased. For security, R2 and R3 must hold the same value.
CPU clock period in nano-seconds (eg. R4 = 50 (32h) means CPU frequency is 20MHz).
CCCCh
EEEEh
DD4sh
AA5sh
55Ash
7777h
R0
BegAddOff
AddOff
AddOff
5555h
5555h
R1
nu
– To read the return values in R0. When the em-
Note: The Flash Embedded STEAK Algorithms
Code examples for programming and erasing the
Flash Memory using STEAK are given in
Section 5.2.
Note For more details refer to STEAK applica-
bedded programming / erasing algorithm returns
to trigger point, return values are given in R0.
Table 6 gives the error-code definitions, Table 7
gives the return values in each register for each
type of Flash programming / erasing command.
require at least 50 words on the Internal
System Stack. STEAK verifies that there is
enough free space on the System Stack,
before performing a programming or eras-
ing operation.The MDH, MDL and MDC
register content are modified.
tion note on www.st.com web site.
EndAddOff
3333h
DWL
Bnk
R2
nu
W
SourceAddr
AAAAh
DWH
Bnk
R3
nu
nu
2TCL
2TCL
2TCL
2TCL
2TCL
2TCL
R4