ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 19

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. Additional hardware has been added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.
Most of the ST10F168’s instructions can be exe-
cuted in one instruction cycle which requires
62.5ns at 32MHz CPU clock. For example, shift
and rotate instructions are processed in one
instruction cycle independent of the number of bit
to be shifted. Multiple-cycle instructions have
been optimized: branches are carried out in 2
cycles, 16 x 16-bit multiplication in 5 cycles and a
32/16 bit division in 10 cycles.The jump cache
reduces the execution time of repeatedly per-
formed jumps in a loop, from 2 cycles to 1 cycle.
Figure 5 : CPU Block Diagram
256K Byte
memory
Flash
32
Exec. Unit
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
Instr. Ptr
Instr. Reg
STKUN
SYSCON
STKOV
Pipeline
PSW
4-Stage
SP
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
Bit-Mask Gen.
Mul./Div.-HW
Barrel-Shift
CPU
16-Bit
MDH
MLD
ALU
CP
The CPU uses a bank of 16 word registers to run
the current context. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip RAM area. A Context Pointer (CP) regis-
ter determines the base address of the active reg-
ister bank to be accessed by the CPU. The
number of register banks is only restricted by the
available internal RAM space. For easy parameter
passing, one register bank may overlap others.
A system stack of up to 2048 Byte stores tempo-
rary data. The system stack is allocated in the
on-chip RAM area, and it is accessed by the CPU
via the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly com-
pared against the stack pointer value on each
stack access, for the detection of a stack overflow
or underflow.
Registers
General
Purpose
R15
R0
16
16
2K Byte
Internal
RAM
ST10F168
Bank
Bank
Bank
n
0
i
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