ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 52

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
Figure 15 : Supply / idle current as a function of operation frequency
20.4 - A/D Converter Characteristics
V
T
Notes: 1. V
52/74
R
R
A
DD
C
V
TUE
Symbol
ASRC
AREF
t
AIN
t
= -40, +85 C and for Q3 version T
AIN
S
C
= 5V 10%, V
X000h or X3FFh, respectively.
2. During the t
the analog source must allow the capacitance to reach its final voltage level within the t
time, changes of the analog input voltage have no effect on the conversion result. Values for the t
programming. Referring to the t
t
t
TCL is defined in section 20.5.5 at page 55.
3. The conversion time formula is:
t
The t
the result of the conversion. Values for the t
to the table below:
t
t
4. This parameter is fixed by ADC control logic.
5. TUE is tested at V
defined voltage range. The specified TUE is guaranteed only if an overload condition (see Iov specification) occurs on maximum of 2
not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
During the reset calibration sequence the maximum TUE may be 4 LSB.
S
S
C
C
C
min = 2 t
max = 2 t
= 14 t
min = 14 t
max = 14 t
SR Analog input voltage range
CC Sample time
CC Conversion time
CC Total unadjusted error
SR Internal resistance of reference voltage source
SR Internal resistance of analog source
CC ADC input capacitance
AIN
C
parameter includes the t
CC
may exceed V
SC
+ t
SC
CC
CC
S
S
min = 2 t
max = 2 x 8 t
sample time the input capacitance C
+ 4 TCL (= 14 t
min + t
max + t
SS
AREF
I [mA]
100
200
= 0V, 4.0V
S
10
CC
AGND
S
min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
= 5.0V, V
min = 2 x 24 x TCL = 48 TCL
CC
or V
Parameter
CC
C
max = 2 x 8 x 96 TCL = 1536 TCL
S
conversion time formula of chapter 13, to the table 17 of page 33 and to the table below:
AREF
sample time, the time for determining the digital result and the time to load the result register with
+ 2 t
AGND
5
SC
up to the absolute maximum ratings. However, the conversion result in these cases will be
V
= 0V, V
A
AREF
+ 4 TCL)
CC
= -40 C, +125 C, unless otherwise specified
conversion clock depend on the programming. Referring to the table 17 of page 33 and
CC
10
= 4.9V. It is guaranteed by design characterization for all other voltages within the
V
ain
DD
can be charged/discharged by the external source. The internal resistance of
+ 0.1V, V
15
t
CC
t
S
Conditions
SS
in [ns]
in [ns]
Test
1 - 8
2 - 4
3 - 4
20
- 0.1V
5
7
2 - 7
6 - 7
I
I
CCmax
IDmax
25
V
388 TCL
S
48 TCL
V
AGND
sample time. After the end of the t
Min.
AGND
–
–
–
–
f
CPU
[MHz]
V
SC
(t
SS
(t
CC
S
sample clock depend on the
1 536 TCL
2 884 TCL
+ 0.2V, Q6 version :
/ 330) - 0.25
/ 165) - 0.25
V
Max.
AREF
33
2
S
sample
Unit
LSB
k
k
pF
V