ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 36

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
15 - CAN MODULE
The integrated CAN module completely handles
the autonomous transmission and the reception of
CAN frames according to the CAN specification
V2.0 part B (active). The on-chip CAN module can
receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit
identifiers.
The CAN Module Provides full CAN functionality
on up to 15 message objects. Message object 15
can be configured for basic CAN functionality.
Both modes provide separate masks for accep-
tance filtering, allowing a number of identifiers in
full CAN mode to be accepted and disregarding a
number of identifiers in basic CAN mode. All mes-
sage objects can be updated independently from
other objects and are equipped for the maximum
message length of 8 Bytes.
The bit timing is derived from the XCLK and is pro-
grammable up to a data rate of 1M Baud. The
CAN module uses two pins to interface to a bus
transceiver.
16 - WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism
which prevents the microcontroller from malfunc-
tioning for long periods of time.
The Watchdog Timer is always enabled after a
reset of the chip and can only be disabled in the
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time interval until the EINIT (end of initialization)
instruction has been executed.
Therefore, the chip start-up procedure is always
monitored. The software must be designed to ser-
vice the watchdog timer before it overflows. If, due
to hardware or software related failures, the soft-
ware fails to do so, the watchdog timer overflows
and generates an internal hardware reset. It pulls
the
hardware components to be reset.
The Watchdog Timer is 16-bit, clocked with the
system clock divided by 2 or 128. The high Byte of
the watchdog timer register can be set to a
pre-specified reload value (stored in WDTREL).
Each time it is serviced by the application soft-
ware, the high Byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each
time before the watchdog timer is serviced.
Table 20 shows the watchdog time range for
25MHz CPU clock.
Table 20 : Watchdog time range (25MHz clock)
Reload value
in WDTREL
RSTOUT
FFh
00h
pin low in order to allow external
2 (WDTIN = ‘0’)
20.48 s
5.24ms
Prescaler for f
128 (WDTIN = ‘1’)
CPU
1.31ms
336ms