ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 54

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
20.5.2 - Definition of Internal Timing
The internal operation of the ST10F168 is
controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (e.g.
pipeline) or external (e.g. bus cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock,
called “TCL” (see Figure 18).
Figure 18 : Generation Mechanisms for the CPU Clock
20.5.3 - Clock Generation Modes
The Table 23 associates the combinations of these three bit with the respective clock generation mode.
Table 23 : CPU Frequency Generation
Notes: 1. The external clock input range refers to a CPU clock range of 1...25MHz.
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P0H.7 P0H.6 P0H.5 CPU Frequency f
1
1
1
1
0
0
0
0
2. The maximum depends on the duty cycle of the external clock signal.
3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial
resistance of the crystal is less than 40 . However, higher frequencies can be applied with an external clock source on pin XTAL1,
but in this case, the input clock signal must reach the defined levels V
1
1
0
0
1
1
0
0
Phase locked loop operation
Direct Clock Drive
Prescaler Operation
1
0
1
0
1
0
1
0
f
f
f
f
f
f
XTAL
CPU
XTAL
CPU
XTAL
CPU
f
f
XTAL
XTAL
f
f
f
f
f
f
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
x 1.5
x 2.5
x 4
x 3
x 2
x 5
x 1
CPU
/ 2
CPU
= f
. Both
XTAL
x F External Clock Inpu t Range
The CPU clock signal can be generated by
different mechanisms. The duration of TCL and its
variation (and also the derived external timing)
depends on the mechanism used to generate
f
calculating the timings for the ST10F168.
The example for PLL operation shown in the
Figure 18 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock
is selected during reset by the logic levels on pins
P0.15-13 (P0H.7-5).
CPU
IL
. This influence must be regarded when
3.33 to 8.33MHz
6.66 to 16.6MHz
and V
2.5 to 6.25MHz
5 to 12.5MHz
1 to 25MHz
2 to 50MHz
4 to 10MHz
2 to 5MHz
IH2.
TCL
TCL
TCL TCL
TCL TCL
1
Default configuration
Direct drive
CPU clock via prescaler
Notes
2
3